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234#![allow(clippy::missing_safety_doc)]
#![allow(clippy::identity_op)]
#![allow(clippy::unnecessary_cast)]
#![allow(clippy::erasing_op)]
# [doc = "System configuration controller"]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Syscfg { ptr : * mut u8 } unsafe impl Send for Syscfg { } unsafe impl Sync for Syscfg { } impl Syscfg { # [inline (always)]
pub const unsafe fn from_ptr (ptr : * mut ()) -> Self { Self { ptr : ptr as _ , } } # [inline (always)]
pub const fn as_ptr (& self) -> * mut () { self . ptr as _ } # [doc = "SYSCFG secure configuration register"]
# [inline (always)]
pub const fn seccfgr (self) -> crate :: common :: Reg < regs :: Seccfgr , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0usize) as _) } } # [doc = "configuration register 1"]
# [inline (always)]
pub const fn cfgr1 (self) -> crate :: common :: Reg < regs :: Cfgr1 , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x04usize) as _) } } # [doc = "FPU interrupt mask register"]
# [inline (always)]
pub const fn fpuimr (self) -> crate :: common :: Reg < regs :: Fpuimr , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x08usize) as _) } } # [doc = "SYSCFG CPU non-secure lock register"]
# [inline (always)]
pub const fn cnslckr (self) -> crate :: common :: Reg < regs :: Cnslckr , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0cusize) as _) } } # [doc = "SYSCFG CPU secure lock register"]
# [inline (always)]
pub const fn cslockr (self) -> crate :: common :: Reg < regs :: Cslockr , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x10usize) as _) } } # [doc = "configuration register 2"]
# [inline (always)]
pub const fn cfgr2 (self) -> crate :: common :: Reg < regs :: Cfgr2 , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x14usize) as _) } } # [doc = "memory erase status register"]
# [inline (always)]
pub const fn mesr (self) -> crate :: common :: Reg < regs :: Mesr , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x18usize) as _) } } # [doc = "compensation cell control/status register"]
# [inline (always)]
pub const fn cccsr (self) -> crate :: common :: Reg < regs :: Cccsr , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x1cusize) as _) } } # [doc = "compensation cell value register"]
# [inline (always)]
pub const fn ccvr (self) -> crate :: common :: Reg < regs :: Ccvr , crate :: common :: R > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x20usize) as _) } } # [doc = "compensation cell code register"]
# [inline (always)]
pub const fn cccr (self) -> crate :: common :: Reg < regs :: Cccr , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x24usize) as _) } } # [doc = "RSS command register"]
# [inline (always)]
pub const fn rsscmdr (self) -> crate :: common :: Reg < regs :: Rsscmdr , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x2cusize) as _) } } # [doc = "USB Type C and Power Delivery register"]
# [inline (always)]
pub const fn ucpdr (self) -> crate :: common :: Reg < regs :: Ucpdr , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x70usize) as _) } } } pub mod regs { # [doc = "compensation cell code register"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Cccr (pub u32) ; impl Cccr { # [doc = "NCC1"]
# [inline (always)]
pub const fn ncc1 (& self) -> u8 { let val = (self . 0 >> 0usize) & 0x0f ; val as u8 } # [doc = "NCC1"]
# [inline (always)]
pub fn set_ncc1 (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize) ; } # [doc = "PCC1"]
# [inline (always)]
pub const fn pcc1 (& self) -> u8 { let val = (self . 0 >> 4usize) & 0x0f ; val as u8 } # [doc = "PCC1"]
# [inline (always)]
pub fn set_pcc1 (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize) ; } # [doc = "NCC2"]
# [inline (always)]
pub const fn ncc2 (& self) -> u8 { let val = (self . 0 >> 8usize) & 0x0f ; val as u8 } # [doc = "NCC2"]
# [inline (always)]
pub fn set_ncc2 (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize) ; } # [doc = "PCC2"]
# [inline (always)]
pub const fn pcc2 (& self) -> u8 { let val = (self . 0 >> 12usize) & 0x0f ; val as u8 } # [doc = "PCC2"]
# [inline (always)]
pub fn set_pcc2 (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x0f << 12usize)) | (((val as u32) & 0x0f) << 12usize) ; } } impl Default for Cccr { # [inline (always)]
fn default () -> Cccr { Cccr (0) } } # [doc = "compensation cell control/status register"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Cccsr (pub u32) ; impl Cccsr { # [doc = "EN1"]
# [inline (always)]
pub const fn en1 (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "EN1"]
# [inline (always)]
pub fn set_en1 (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "CS1"]
# [inline (always)]
pub const fn cs1 (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "CS1"]
# [inline (always)]
pub fn set_cs1 (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "EN2"]
# [inline (always)]
pub const fn en2 (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "EN2"]
# [inline (always)]
pub fn set_en2 (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } # [doc = "CS2"]
# [inline (always)]
pub const fn cs2 (& self) -> bool { let val = (self . 0 >> 3usize) & 0x01 ; val != 0 } # [doc = "CS2"]
# [inline (always)]
pub fn set_cs2 (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize) ; } # [doc = "RDY1"]
# [inline (always)]
pub const fn rdy1 (& self) -> bool { let val = (self . 0 >> 8usize) & 0x01 ; val != 0 } # [doc = "RDY1"]
# [inline (always)]
pub fn set_rdy1 (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize) ; } # [doc = "RDY2"]
# [inline (always)]
pub const fn rdy2 (& self) -> bool { let val = (self . 0 >> 9usize) & 0x01 ; val != 0 } # [doc = "RDY2"]
# [inline (always)]
pub fn set_rdy2 (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize) ; } } impl Default for Cccsr { # [inline (always)]
fn default () -> Cccsr { Cccsr (0) } } # [doc = "compensation cell value register"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Ccvr (pub u32) ; impl Ccvr { # [doc = "NCV1"]
# [inline (always)]
pub const fn ncv1 (& self) -> u8 { let val = (self . 0 >> 0usize) & 0x0f ; val as u8 } # [doc = "NCV1"]
# [inline (always)]
pub fn set_ncv1 (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize) ; } # [doc = "PCV1"]
# [inline (always)]
pub const fn pcv1 (& self) -> u8 { let val = (self . 0 >> 4usize) & 0x0f ; val as u8 } # [doc = "PCV1"]
# [inline (always)]
pub fn set_pcv1 (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize) ; } # [doc = "NCV2"]
# [inline (always)]
pub const fn ncv2 (& self) -> u8 { let val = (self . 0 >> 8usize) & 0x0f ; val as u8 } # [doc = "NCV2"]
# [inline (always)]
pub fn set_ncv2 (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize) ; } # [doc = "PCV2"]
# [inline (always)]
pub const fn pcv2 (& self) -> u8 { let val = (self . 0 >> 12usize) & 0x0f ; val as u8 } # [doc = "PCV2"]
# [inline (always)]
pub fn set_pcv2 (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x0f << 12usize)) | (((val as u32) & 0x0f) << 12usize) ; } } impl Default for Ccvr { # [inline (always)]
fn default () -> Ccvr { Ccvr (0) } } # [doc = "configuration register 1"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Cfgr1 (pub u32) ; impl Cfgr1 { # [doc = "I/O analog switch voltage booster enable"]
# [inline (always)]
pub const fn boosten (& self) -> bool { let val = (self . 0 >> 8usize) & 0x01 ; val != 0 } # [doc = "I/O analog switch voltage booster enable"]
# [inline (always)]
pub fn set_boosten (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize) ; } # [doc = "GPIO analog switch control voltage selection"]
# [inline (always)]
pub const fn anaswvdd (& self) -> bool { let val = (self . 0 >> 9usize) & 0x01 ; val != 0 } # [doc = "GPIO analog switch control voltage selection"]
# [inline (always)]
pub fn set_anaswvdd (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize) ; } # [doc = "PB6_FMP"]
# [inline (always)]
pub const fn pb6_fmp (& self) -> bool { let val = (self . 0 >> 16usize) & 0x01 ; val != 0 } # [doc = "PB6_FMP"]
# [inline (always)]
pub fn set_pb6_fmp (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize) ; } # [doc = "PB7_FMP"]
# [inline (always)]
pub const fn pb7_fmp (& self) -> bool { let val = (self . 0 >> 17usize) & 0x01 ; val != 0 } # [doc = "PB7_FMP"]
# [inline (always)]
pub fn set_pb7_fmp (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize) ; } # [doc = "PB8_FMP"]
# [inline (always)]
pub const fn pb8_fmp (& self) -> bool { let val = (self . 0 >> 18usize) & 0x01 ; val != 0 } # [doc = "PB8_FMP"]
# [inline (always)]
pub fn set_pb8_fmp (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize) ; } # [doc = "PB9_FMP"]
# [inline (always)]
pub const fn pb9_fmp (& self) -> bool { let val = (self . 0 >> 19usize) & 0x01 ; val != 0 } # [doc = "PB9_FMP"]
# [inline (always)]
pub fn set_pb9_fmp (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize) ; } } impl Default for Cfgr1 { # [inline (always)]
fn default () -> Cfgr1 { Cfgr1 (0) } } # [doc = "configuration register 2"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Cfgr2 (pub u32) ; impl Cfgr2 { # [doc = "LOCKUP (hardfault) output enable bit"]
# [inline (always)]
pub const fn cll (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "LOCKUP (hardfault) output enable bit"]
# [inline (always)]
pub fn set_cll (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "SRAM ECC lock bit"]
# [inline (always)]
pub const fn spl (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "SRAM ECC lock bit"]
# [inline (always)]
pub fn set_spl (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "PVD lock enable bit"]
# [inline (always)]
pub const fn pvdl (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "PVD lock enable bit"]
# [inline (always)]
pub fn set_pvdl (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } # [doc = "ECC Lock"]
# [inline (always)]
pub const fn eccl (& self) -> bool { let val = (self . 0 >> 3usize) & 0x01 ; val != 0 } # [doc = "ECC Lock"]
# [inline (always)]
pub fn set_eccl (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize) ; } } impl Default for Cfgr2 { # [inline (always)]
fn default () -> Cfgr2 { Cfgr2 (0) } } # [doc = "SYSCFG CPU non-secure lock register"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Cnslckr (pub u32) ; impl Cnslckr { # [doc = "VTOR_NS register lock"]
# [inline (always)]
pub const fn locknsvtor (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "VTOR_NS register lock"]
# [inline (always)]
pub fn set_locknsvtor (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "Non-secure MPU registers lock"]
# [inline (always)]
pub const fn locknsmpu (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "Non-secure MPU registers lock"]
# [inline (always)]
pub fn set_locknsmpu (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } } impl Default for Cnslckr { # [inline (always)]
fn default () -> Cnslckr { Cnslckr (0) } } # [doc = "SYSCFG CPU secure lock register"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Cslockr (pub u32) ; impl Cslockr { # [doc = "LOCKSVTAIRCR"]
# [inline (always)]
pub const fn locksvtaircr (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "LOCKSVTAIRCR"]
# [inline (always)]
pub fn set_locksvtaircr (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "LOCKSMPU"]
# [inline (always)]
pub const fn locksmpu (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "LOCKSMPU"]
# [inline (always)]
pub fn set_locksmpu (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "LOCKSAU"]
# [inline (always)]
pub const fn locksau (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "LOCKSAU"]
# [inline (always)]
pub fn set_locksau (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } } impl Default for Cslockr { # [inline (always)]
fn default () -> Cslockr { Cslockr (0) } } # [doc = "FPU interrupt mask register"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Fpuimr (pub u32) ; impl Fpuimr { # [doc = "Floating point unit interrupts enable bits"]
# [inline (always)]
pub const fn fpu_ie (& self) -> u8 { let val = (self . 0 >> 0usize) & 0x3f ; val as u8 } # [doc = "Floating point unit interrupts enable bits"]
# [inline (always)]
pub fn set_fpu_ie (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize) ; } } impl Default for Fpuimr { # [inline (always)]
fn default () -> Fpuimr { Fpuimr (0) } } # [doc = "memory erase status register"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Mesr (pub u32) ; impl Mesr { # [doc = "MCLR"]
# [inline (always)]
pub const fn mclr (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "MCLR"]
# [inline (always)]
pub fn set_mclr (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "IPMEE"]
# [inline (always)]
pub const fn ipmee (& self) -> bool { let val = (self . 0 >> 16usize) & 0x01 ; val != 0 } # [doc = "IPMEE"]
# [inline (always)]
pub fn set_ipmee (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize) ; } } impl Default for Mesr { # [inline (always)]
fn default () -> Mesr { Mesr (0) } } # [doc = "RSS command register"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Rsscmdr (pub u32) ; impl Rsscmdr { # [doc = "RSS commands"]
# [inline (always)]
pub const fn rsscmd (& self) -> u16 { let val = (self . 0 >> 0usize) & 0xffff ; val as u16 } # [doc = "RSS commands"]
# [inline (always)]
pub fn set_rsscmd (& mut self , val : u16) { self . 0 = (self . 0 & ! (0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize) ; } } impl Default for Rsscmdr { # [inline (always)]
fn default () -> Rsscmdr { Rsscmdr (0) } } # [doc = "SYSCFG secure configuration register"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Seccfgr (pub u32) ; impl Seccfgr { # [doc = "SYSCFG clock control security"]
# [inline (always)]
pub const fn syscfgsec (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "SYSCFG clock control security"]
# [inline (always)]
pub fn set_syscfgsec (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "CLASSBSEC"]
# [inline (always)]
pub const fn classbsec (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "CLASSBSEC"]
# [inline (always)]
pub fn set_classbsec (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "FPUSEC"]
# [inline (always)]
pub const fn fpusec (& self) -> bool { let val = (self . 0 >> 3usize) & 0x01 ; val != 0 } # [doc = "FPUSEC"]
# [inline (always)]
pub fn set_fpusec (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize) ; } } impl Default for Seccfgr { # [inline (always)]
fn default () -> Seccfgr { Seccfgr (0) } } # [doc = "USB Type C and Power Delivery register"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Ucpdr (pub u32) ; impl Ucpdr { # [doc = "CC1ENRXFILTER"]
# [inline (always)]
pub const fn cc1enrxfilter (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "CC1ENRXFILTER"]
# [inline (always)]
pub fn set_cc1enrxfilter (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "CC2ENRXFILTER"]
# [inline (always)]
pub const fn cc2enrxfilter (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "CC2ENRXFILTER"]
# [inline (always)]
pub fn set_cc2enrxfilter (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } } impl Default for Ucpdr { # [inline (always)]
fn default () -> Ucpdr { Ucpdr (0) } } }