📦 samueltardieu / stm32-metapac-generated

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930#![allow(clippy::missing_safety_doc)]
                #![allow(clippy::identity_op)]
                #![allow(clippy::unnecessary_cast)]
                #![allow(clippy::erasing_op)]

# [doc = "Reset and clock control"]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Rcc { ptr : * mut u8 } unsafe impl Send for Rcc { } unsafe impl Sync for Rcc { } impl Rcc { # [inline (always)]
pub const unsafe fn from_ptr (ptr : * mut ()) -> Self { Self { ptr : ptr as _ , } } # [inline (always)]
pub const fn as_ptr (& self) -> * mut () { self . ptr as _ } # [doc = "Clock control register"]
# [inline (always)]
pub const fn cr (self) -> crate :: common :: Reg < regs :: Cr , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0usize) as _) } } # [doc = "Clock configuration register (RCC_CFGR)"]
# [inline (always)]
pub const fn cfgr (self) -> crate :: common :: Reg < regs :: Cfgr , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x04usize) as _) } } # [doc = "Clock interrupt register (RCC_CIR)"]
# [inline (always)]
pub const fn cir (self) -> crate :: common :: Reg < regs :: Cir , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x08usize) as _) } } # [doc = "APB2 peripheral reset register (RCC_APB2RSTR)"]
# [inline (always)]
pub const fn apb2rstr (self) -> crate :: common :: Reg < regs :: Apb2rstr , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0cusize) as _) } } # [doc = "APB1 peripheral reset register (RCC_APB1RSTR)"]
# [inline (always)]
pub const fn apb1rstr (self) -> crate :: common :: Reg < regs :: Apb1rstr , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x10usize) as _) } } # [doc = "AHB Peripheral Clock enable register (RCC_AHBENR)"]
# [inline (always)]
pub const fn ahbenr (self) -> crate :: common :: Reg < regs :: Ahbenr , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x14usize) as _) } } # [doc = "APB2 peripheral clock enable register (RCC_APB2ENR)"]
# [inline (always)]
pub const fn apb2enr (self) -> crate :: common :: Reg < regs :: Apb2enr , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x18usize) as _) } } # [doc = "APB1 peripheral clock enable register (RCC_APB1ENR)"]
# [inline (always)]
pub const fn apb1enr (self) -> crate :: common :: Reg < regs :: Apb1enr , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x1cusize) as _) } } # [doc = "Backup domain control register (RCC_BDCR)"]
# [inline (always)]
pub const fn bdcr (self) -> crate :: common :: Reg < regs :: Bdcr , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x20usize) as _) } } # [doc = "Control/status register (RCC_CSR)"]
# [inline (always)]
pub const fn csr (self) -> crate :: common :: Reg < regs :: Csr , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x24usize) as _) } } # [doc = "AHB peripheral reset register"]
# [inline (always)]
pub const fn ahbrstr (self) -> crate :: common :: Reg < regs :: Ahbrstr , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x28usize) as _) } } # [doc = "Clock configuration register 2"]
# [inline (always)]
pub const fn cfgr2 (self) -> crate :: common :: Reg < regs :: Cfgr2 , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x2cusize) as _) } } # [doc = "Clock configuration register 3"]
# [inline (always)]
pub const fn cfgr3 (self) -> crate :: common :: Reg < regs :: Cfgr3 , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x30usize) as _) } } # [doc = "Clock control register 2"]
# [inline (always)]
pub const fn cr2 (self) -> crate :: common :: Reg < regs :: Cr2 , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x34usize) as _) } } } pub mod regs { # [doc = "AHB Peripheral Clock enable register (RCC_AHBENR)"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Ahbenr (pub u32) ; impl Ahbenr { # [doc = "DMA clock enable"]
# [inline (always)]
pub const fn dmaen (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "DMA clock enable"]
# [inline (always)]
pub fn set_dmaen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "DMA2 clock enable"]
# [inline (always)]
pub const fn dma2en (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "DMA2 clock enable"]
# [inline (always)]
pub fn set_dma2en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "SRAM interface clock enable"]
# [inline (always)]
pub const fn sramen (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "SRAM interface clock enable"]
# [inline (always)]
pub fn set_sramen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } # [doc = "FLASH clock enable"]
# [inline (always)]
pub const fn flashen (& self) -> bool { let val = (self . 0 >> 4usize) & 0x01 ; val != 0 } # [doc = "FLASH clock enable"]
# [inline (always)]
pub fn set_flashen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize) ; } # [doc = "CRC clock enable"]
# [inline (always)]
pub const fn crcen (& self) -> bool { let val = (self . 0 >> 6usize) & 0x01 ; val != 0 } # [doc = "CRC clock enable"]
# [inline (always)]
pub fn set_crcen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize) ; } # [doc = "I/O port A clock enable"]
# [inline (always)]
pub const fn gpioaen (& self) -> bool { let val = (self . 0 >> 17usize) & 0x01 ; val != 0 } # [doc = "I/O port A clock enable"]
# [inline (always)]
pub fn set_gpioaen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize) ; } # [doc = "I/O port B clock enable"]
# [inline (always)]
pub const fn gpioben (& self) -> bool { let val = (self . 0 >> 18usize) & 0x01 ; val != 0 } # [doc = "I/O port B clock enable"]
# [inline (always)]
pub fn set_gpioben (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize) ; } # [doc = "I/O port C clock enable"]
# [inline (always)]
pub const fn gpiocen (& self) -> bool { let val = (self . 0 >> 19usize) & 0x01 ; val != 0 } # [doc = "I/O port C clock enable"]
# [inline (always)]
pub fn set_gpiocen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize) ; } # [doc = "I/O port D clock enable"]
# [inline (always)]
pub const fn gpioden (& self) -> bool { let val = (self . 0 >> 20usize) & 0x01 ; val != 0 } # [doc = "I/O port D clock enable"]
# [inline (always)]
pub fn set_gpioden (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize) ; } # [doc = "I/O port E clock enable"]
# [inline (always)]
pub const fn gpioeen (& self) -> bool { let val = (self . 0 >> 21usize) & 0x01 ; val != 0 } # [doc = "I/O port E clock enable"]
# [inline (always)]
pub fn set_gpioeen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize) ; } # [doc = "I/O port F clock enable"]
# [inline (always)]
pub const fn gpiofen (& self) -> bool { let val = (self . 0 >> 22usize) & 0x01 ; val != 0 } # [doc = "I/O port F clock enable"]
# [inline (always)]
pub fn set_gpiofen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize) ; } # [doc = "Touch sensing controller clock enable"]
# [inline (always)]
pub const fn tscen (& self) -> bool { let val = (self . 0 >> 24usize) & 0x01 ; val != 0 } # [doc = "Touch sensing controller clock enable"]
# [inline (always)]
pub fn set_tscen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize) ; } } impl Default for Ahbenr { # [inline (always)]
fn default () -> Ahbenr { Ahbenr (0) } } # [doc = "AHB peripheral reset register"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Ahbrstr (pub u32) ; impl Ahbrstr { # [doc = "I/O port A reset"]
# [inline (always)]
pub const fn gpioarst (& self) -> bool { let val = (self . 0 >> 17usize) & 0x01 ; val != 0 } # [doc = "I/O port A reset"]
# [inline (always)]
pub fn set_gpioarst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize) ; } # [doc = "I/O port B reset"]
# [inline (always)]
pub const fn gpiobrst (& self) -> bool { let val = (self . 0 >> 18usize) & 0x01 ; val != 0 } # [doc = "I/O port B reset"]
# [inline (always)]
pub fn set_gpiobrst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize) ; } # [doc = "I/O port C reset"]
# [inline (always)]
pub const fn gpiocrst (& self) -> bool { let val = (self . 0 >> 19usize) & 0x01 ; val != 0 } # [doc = "I/O port C reset"]
# [inline (always)]
pub fn set_gpiocrst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize) ; } # [doc = "I/O port D reset"]
# [inline (always)]
pub const fn gpiodrst (& self) -> bool { let val = (self . 0 >> 20usize) & 0x01 ; val != 0 } # [doc = "I/O port D reset"]
# [inline (always)]
pub fn set_gpiodrst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize) ; } # [doc = "I/O port E reset"]
# [inline (always)]
pub const fn gpioerst (& self) -> bool { let val = (self . 0 >> 21usize) & 0x01 ; val != 0 } # [doc = "I/O port E reset"]
# [inline (always)]
pub fn set_gpioerst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize) ; } # [doc = "I/O port F reset"]
# [inline (always)]
pub const fn gpiofrst (& self) -> bool { let val = (self . 0 >> 22usize) & 0x01 ; val != 0 } # [doc = "I/O port F reset"]
# [inline (always)]
pub fn set_gpiofrst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize) ; } # [doc = "Touch sensing controller reset"]
# [inline (always)]
pub const fn tscrst (& self) -> bool { let val = (self . 0 >> 24usize) & 0x01 ; val != 0 } # [doc = "Touch sensing controller reset"]
# [inline (always)]
pub fn set_tscrst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize) ; } } impl Default for Ahbrstr { # [inline (always)]
fn default () -> Ahbrstr { Ahbrstr (0) } } # [doc = "APB1 peripheral clock enable register (RCC_APB1ENR)"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Apb1enr (pub u32) ; impl Apb1enr { # [doc = "Timer 2 clock enable"]
# [inline (always)]
pub const fn tim2en (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "Timer 2 clock enable"]
# [inline (always)]
pub fn set_tim2en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "Timer 3 clock enable"]
# [inline (always)]
pub const fn tim3en (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "Timer 3 clock enable"]
# [inline (always)]
pub fn set_tim3en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "Timer 6 clock enable"]
# [inline (always)]
pub const fn tim6en (& self) -> bool { let val = (self . 0 >> 4usize) & 0x01 ; val != 0 } # [doc = "Timer 6 clock enable"]
# [inline (always)]
pub fn set_tim6en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize) ; } # [doc = "TIM7 timer clock enable"]
# [inline (always)]
pub const fn tim7en (& self) -> bool { let val = (self . 0 >> 5usize) & 0x01 ; val != 0 } # [doc = "TIM7 timer clock enable"]
# [inline (always)]
pub fn set_tim7en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize) ; } # [doc = "Timer 14 clock enable"]
# [inline (always)]
pub const fn tim14en (& self) -> bool { let val = (self . 0 >> 8usize) & 0x01 ; val != 0 } # [doc = "Timer 14 clock enable"]
# [inline (always)]
pub fn set_tim14en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize) ; } # [doc = "Window watchdog clock enable"]
# [inline (always)]
pub const fn wwdgen (& self) -> bool { let val = (self . 0 >> 11usize) & 0x01 ; val != 0 } # [doc = "Window watchdog clock enable"]
# [inline (always)]
pub fn set_wwdgen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize) ; } # [doc = "SPI 2 clock enable"]
# [inline (always)]
pub const fn spi2en (& self) -> bool { let val = (self . 0 >> 14usize) & 0x01 ; val != 0 } # [doc = "SPI 2 clock enable"]
# [inline (always)]
pub fn set_spi2en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize) ; } # [doc = "USART 2 clock enable"]
# [inline (always)]
pub const fn usart2en (& self) -> bool { let val = (self . 0 >> 17usize) & 0x01 ; val != 0 } # [doc = "USART 2 clock enable"]
# [inline (always)]
pub fn set_usart2en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize) ; } # [doc = "USART3 clock enable"]
# [inline (always)]
pub const fn usart3en (& self) -> bool { let val = (self . 0 >> 18usize) & 0x01 ; val != 0 } # [doc = "USART3 clock enable"]
# [inline (always)]
pub fn set_usart3en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize) ; } # [doc = "USART4 clock enable"]
# [inline (always)]
pub const fn usart4en (& self) -> bool { let val = (self . 0 >> 19usize) & 0x01 ; val != 0 } # [doc = "USART4 clock enable"]
# [inline (always)]
pub fn set_usart4en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize) ; } # [doc = "USART5 clock enable"]
# [inline (always)]
pub const fn usart5en (& self) -> bool { let val = (self . 0 >> 20usize) & 0x01 ; val != 0 } # [doc = "USART5 clock enable"]
# [inline (always)]
pub fn set_usart5en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize) ; } # [doc = "I2C 1 clock enable"]
# [inline (always)]
pub const fn i2c1en (& self) -> bool { let val = (self . 0 >> 21usize) & 0x01 ; val != 0 } # [doc = "I2C 1 clock enable"]
# [inline (always)]
pub fn set_i2c1en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize) ; } # [doc = "I2C 2 clock enable"]
# [inline (always)]
pub const fn i2c2en (& self) -> bool { let val = (self . 0 >> 22usize) & 0x01 ; val != 0 } # [doc = "I2C 2 clock enable"]
# [inline (always)]
pub fn set_i2c2en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize) ; } # [doc = "USB interface clock enable"]
# [inline (always)]
pub const fn usben (& self) -> bool { let val = (self . 0 >> 23usize) & 0x01 ; val != 0 } # [doc = "USB interface clock enable"]
# [inline (always)]
pub fn set_usben (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize) ; } # [doc = "CAN interface clock enable"]
# [inline (always)]
pub const fn canen (& self) -> bool { let val = (self . 0 >> 25usize) & 0x01 ; val != 0 } # [doc = "CAN interface clock enable"]
# [inline (always)]
pub fn set_canen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize) ; } # [doc = "Clock Recovery System interface clock enable"]
# [inline (always)]
pub const fn crsen (& self) -> bool { let val = (self . 0 >> 27usize) & 0x01 ; val != 0 } # [doc = "Clock Recovery System interface clock enable"]
# [inline (always)]
pub fn set_crsen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize) ; } # [doc = "Power interface clock enable"]
# [inline (always)]
pub const fn pwren (& self) -> bool { let val = (self . 0 >> 28usize) & 0x01 ; val != 0 } # [doc = "Power interface clock enable"]
# [inline (always)]
pub fn set_pwren (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize) ; } # [doc = "DAC interface clock enable"]
# [inline (always)]
pub const fn dacen (& self) -> bool { let val = (self . 0 >> 29usize) & 0x01 ; val != 0 } # [doc = "DAC interface clock enable"]
# [inline (always)]
pub fn set_dacen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize) ; } # [doc = "HDMI CEC interface clock enable"]
# [inline (always)]
pub const fn cecen (& self) -> bool { let val = (self . 0 >> 30usize) & 0x01 ; val != 0 } # [doc = "HDMI CEC interface clock enable"]
# [inline (always)]
pub fn set_cecen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize) ; } } impl Default for Apb1enr { # [inline (always)]
fn default () -> Apb1enr { Apb1enr (0) } } # [doc = "APB1 peripheral reset register (RCC_APB1RSTR)"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Apb1rstr (pub u32) ; impl Apb1rstr { # [doc = "Timer 2 reset"]
# [inline (always)]
pub const fn tim2rst (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "Timer 2 reset"]
# [inline (always)]
pub fn set_tim2rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "Timer 3 reset"]
# [inline (always)]
pub const fn tim3rst (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "Timer 3 reset"]
# [inline (always)]
pub fn set_tim3rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "Timer 6 reset"]
# [inline (always)]
pub const fn tim6rst (& self) -> bool { let val = (self . 0 >> 4usize) & 0x01 ; val != 0 } # [doc = "Timer 6 reset"]
# [inline (always)]
pub fn set_tim6rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize) ; } # [doc = "TIM7 timer reset"]
# [inline (always)]
pub const fn tim7rst (& self) -> bool { let val = (self . 0 >> 5usize) & 0x01 ; val != 0 } # [doc = "TIM7 timer reset"]
# [inline (always)]
pub fn set_tim7rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize) ; } # [doc = "Timer 14 reset"]
# [inline (always)]
pub const fn tim14rst (& self) -> bool { let val = (self . 0 >> 8usize) & 0x01 ; val != 0 } # [doc = "Timer 14 reset"]
# [inline (always)]
pub fn set_tim14rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize) ; } # [doc = "Window watchdog reset"]
# [inline (always)]
pub const fn wwdgrst (& self) -> bool { let val = (self . 0 >> 11usize) & 0x01 ; val != 0 } # [doc = "Window watchdog reset"]
# [inline (always)]
pub fn set_wwdgrst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize) ; } # [doc = "SPI2 reset"]
# [inline (always)]
pub const fn spi2rst (& self) -> bool { let val = (self . 0 >> 14usize) & 0x01 ; val != 0 } # [doc = "SPI2 reset"]
# [inline (always)]
pub fn set_spi2rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize) ; } # [doc = "USART 2 reset"]
# [inline (always)]
pub const fn usart2rst (& self) -> bool { let val = (self . 0 >> 17usize) & 0x01 ; val != 0 } # [doc = "USART 2 reset"]
# [inline (always)]
pub fn set_usart2rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize) ; } # [doc = "USART3 reset"]
# [inline (always)]
pub const fn usart3rst (& self) -> bool { let val = (self . 0 >> 18usize) & 0x01 ; val != 0 } # [doc = "USART3 reset"]
# [inline (always)]
pub fn set_usart3rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize) ; } # [doc = "USART4 reset"]
# [inline (always)]
pub const fn usart4rst (& self) -> bool { let val = (self . 0 >> 19usize) & 0x01 ; val != 0 } # [doc = "USART4 reset"]
# [inline (always)]
pub fn set_usart4rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize) ; } # [doc = "USART5 reset"]
# [inline (always)]
pub const fn usart5rst (& self) -> bool { let val = (self . 0 >> 20usize) & 0x01 ; val != 0 } # [doc = "USART5 reset"]
# [inline (always)]
pub fn set_usart5rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize) ; } # [doc = "I2C1 reset"]
# [inline (always)]
pub const fn i2c1rst (& self) -> bool { let val = (self . 0 >> 21usize) & 0x01 ; val != 0 } # [doc = "I2C1 reset"]
# [inline (always)]
pub fn set_i2c1rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize) ; } # [doc = "I2C2 reset"]
# [inline (always)]
pub const fn i2c2rst (& self) -> bool { let val = (self . 0 >> 22usize) & 0x01 ; val != 0 } # [doc = "I2C2 reset"]
# [inline (always)]
pub fn set_i2c2rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize) ; } # [doc = "USB interface reset"]
# [inline (always)]
pub const fn usbrst (& self) -> bool { let val = (self . 0 >> 23usize) & 0x01 ; val != 0 } # [doc = "USB interface reset"]
# [inline (always)]
pub fn set_usbrst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize) ; } # [doc = "CAN interface reset"]
# [inline (always)]
pub const fn canrst (& self) -> bool { let val = (self . 0 >> 25usize) & 0x01 ; val != 0 } # [doc = "CAN interface reset"]
# [inline (always)]
pub fn set_canrst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize) ; } # [doc = "Clock Recovery System interface reset"]
# [inline (always)]
pub const fn crsrst (& self) -> bool { let val = (self . 0 >> 27usize) & 0x01 ; val != 0 } # [doc = "Clock Recovery System interface reset"]
# [inline (always)]
pub fn set_crsrst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize) ; } # [doc = "Power interface reset"]
# [inline (always)]
pub const fn pwrrst (& self) -> bool { let val = (self . 0 >> 28usize) & 0x01 ; val != 0 } # [doc = "Power interface reset"]
# [inline (always)]
pub fn set_pwrrst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize) ; } # [doc = "DAC interface reset"]
# [inline (always)]
pub const fn dacrst (& self) -> bool { let val = (self . 0 >> 29usize) & 0x01 ; val != 0 } # [doc = "DAC interface reset"]
# [inline (always)]
pub fn set_dacrst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize) ; } # [doc = "HDMI CEC reset"]
# [inline (always)]
pub const fn cecrst (& self) -> bool { let val = (self . 0 >> 30usize) & 0x01 ; val != 0 } # [doc = "HDMI CEC reset"]
# [inline (always)]
pub fn set_cecrst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize) ; } } impl Default for Apb1rstr { # [inline (always)]
fn default () -> Apb1rstr { Apb1rstr (0) } } # [doc = "APB2 peripheral clock enable register (RCC_APB2ENR)"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Apb2enr (pub u32) ; impl Apb2enr { # [doc = "SYSCFG clock enable"]
# [inline (always)]
pub const fn syscfgen (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "SYSCFG clock enable"]
# [inline (always)]
pub fn set_syscfgen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "USART6 clock enable"]
# [inline (always)]
pub const fn usart6en (& self) -> bool { let val = (self . 0 >> 5usize) & 0x01 ; val != 0 } # [doc = "USART6 clock enable"]
# [inline (always)]
pub fn set_usart6en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize) ; } # [doc = "USART7 clock enable"]
# [inline (always)]
pub const fn usart7en (& self) -> bool { let val = (self . 0 >> 6usize) & 0x01 ; val != 0 } # [doc = "USART7 clock enable"]
# [inline (always)]
pub fn set_usart7en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize) ; } # [doc = "USART8 clock enable"]
# [inline (always)]
pub const fn usart8en (& self) -> bool { let val = (self . 0 >> 7usize) & 0x01 ; val != 0 } # [doc = "USART8 clock enable"]
# [inline (always)]
pub fn set_usart8en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize) ; } # [doc = "ADC 1 interface clock enable"]
# [inline (always)]
pub const fn adcen (& self) -> bool { let val = (self . 0 >> 9usize) & 0x01 ; val != 0 } # [doc = "ADC 1 interface clock enable"]
# [inline (always)]
pub fn set_adcen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize) ; } # [doc = "TIM1 Timer clock enable"]
# [inline (always)]
pub const fn tim1en (& self) -> bool { let val = (self . 0 >> 11usize) & 0x01 ; val != 0 } # [doc = "TIM1 Timer clock enable"]
# [inline (always)]
pub fn set_tim1en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize) ; } # [doc = "SPI 1 clock enable"]
# [inline (always)]
pub const fn spi1en (& self) -> bool { let val = (self . 0 >> 12usize) & 0x01 ; val != 0 } # [doc = "SPI 1 clock enable"]
# [inline (always)]
pub fn set_spi1en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize) ; } # [doc = "USART1 clock enable"]
# [inline (always)]
pub const fn usart1en (& self) -> bool { let val = (self . 0 >> 14usize) & 0x01 ; val != 0 } # [doc = "USART1 clock enable"]
# [inline (always)]
pub fn set_usart1en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize) ; } # [doc = "TIM15 timer clock enable"]
# [inline (always)]
pub const fn tim15en (& self) -> bool { let val = (self . 0 >> 16usize) & 0x01 ; val != 0 } # [doc = "TIM15 timer clock enable"]
# [inline (always)]
pub fn set_tim15en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize) ; } # [doc = "TIM16 timer clock enable"]
# [inline (always)]
pub const fn tim16en (& self) -> bool { let val = (self . 0 >> 17usize) & 0x01 ; val != 0 } # [doc = "TIM16 timer clock enable"]
# [inline (always)]
pub fn set_tim16en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize) ; } # [doc = "TIM17 timer clock enable"]
# [inline (always)]
pub const fn tim17en (& self) -> bool { let val = (self . 0 >> 18usize) & 0x01 ; val != 0 } # [doc = "TIM17 timer clock enable"]
# [inline (always)]
pub fn set_tim17en (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize) ; } # [doc = "MCU debug module clock enable"]
# [inline (always)]
pub const fn dbgmcuen (& self) -> bool { let val = (self . 0 >> 22usize) & 0x01 ; val != 0 } # [doc = "MCU debug module clock enable"]
# [inline (always)]
pub fn set_dbgmcuen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize) ; } } impl Default for Apb2enr { # [inline (always)]
fn default () -> Apb2enr { Apb2enr (0) } } # [doc = "APB2 peripheral reset register (RCC_APB2RSTR)"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Apb2rstr (pub u32) ; impl Apb2rstr { # [doc = "SYSCFG and COMP reset"]
# [inline (always)]
pub const fn syscfgrst (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "SYSCFG and COMP reset"]
# [inline (always)]
pub fn set_syscfgrst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "USART6 reset"]
# [inline (always)]
pub const fn usart6rst (& self) -> bool { let val = (self . 0 >> 5usize) & 0x01 ; val != 0 } # [doc = "USART6 reset"]
# [inline (always)]
pub fn set_usart6rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize) ; } # [doc = "USART7 reset"]
# [inline (always)]
pub const fn usart7rst (& self) -> bool { let val = (self . 0 >> 6usize) & 0x01 ; val != 0 } # [doc = "USART7 reset"]
# [inline (always)]
pub fn set_usart7rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize) ; } # [doc = "USART8 reset"]
# [inline (always)]
pub const fn usart8rst (& self) -> bool { let val = (self . 0 >> 7usize) & 0x01 ; val != 0 } # [doc = "USART8 reset"]
# [inline (always)]
pub fn set_usart8rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize) ; } # [doc = "ADC interface reset"]
# [inline (always)]
pub const fn adcrst (& self) -> bool { let val = (self . 0 >> 9usize) & 0x01 ; val != 0 } # [doc = "ADC interface reset"]
# [inline (always)]
pub fn set_adcrst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize) ; } # [doc = "TIM1 timer reset"]
# [inline (always)]
pub const fn tim1rst (& self) -> bool { let val = (self . 0 >> 11usize) & 0x01 ; val != 0 } # [doc = "TIM1 timer reset"]
# [inline (always)]
pub fn set_tim1rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize) ; } # [doc = "SPI 1 reset"]
# [inline (always)]
pub const fn spi1rst (& self) -> bool { let val = (self . 0 >> 12usize) & 0x01 ; val != 0 } # [doc = "SPI 1 reset"]
# [inline (always)]
pub fn set_spi1rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize) ; } # [doc = "USART1 reset"]
# [inline (always)]
pub const fn usart1rst (& self) -> bool { let val = (self . 0 >> 14usize) & 0x01 ; val != 0 } # [doc = "USART1 reset"]
# [inline (always)]
pub fn set_usart1rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize) ; } # [doc = "TIM15 timer reset"]
# [inline (always)]
pub const fn tim15rst (& self) -> bool { let val = (self . 0 >> 16usize) & 0x01 ; val != 0 } # [doc = "TIM15 timer reset"]
# [inline (always)]
pub fn set_tim15rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize) ; } # [doc = "TIM16 timer reset"]
# [inline (always)]
pub const fn tim16rst (& self) -> bool { let val = (self . 0 >> 17usize) & 0x01 ; val != 0 } # [doc = "TIM16 timer reset"]
# [inline (always)]
pub fn set_tim16rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize) ; } # [doc = "TIM17 timer reset"]
# [inline (always)]
pub const fn tim17rst (& self) -> bool { let val = (self . 0 >> 18usize) & 0x01 ; val != 0 } # [doc = "TIM17 timer reset"]
# [inline (always)]
pub fn set_tim17rst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize) ; } # [doc = "Debug MCU reset"]
# [inline (always)]
pub const fn dbgmcurst (& self) -> bool { let val = (self . 0 >> 22usize) & 0x01 ; val != 0 } # [doc = "Debug MCU reset"]
# [inline (always)]
pub fn set_dbgmcurst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize) ; } } impl Default for Apb2rstr { # [inline (always)]
fn default () -> Apb2rstr { Apb2rstr (0) } } # [doc = "Backup domain control register (RCC_BDCR)"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Bdcr (pub u32) ; impl Bdcr { # [doc = "External Low Speed oscillator enable"]
# [inline (always)]
pub const fn lseon (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "External Low Speed oscillator enable"]
# [inline (always)]
pub fn set_lseon (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "External Low Speed oscillator ready"]
# [inline (always)]
pub const fn lserdy (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "External Low Speed oscillator ready"]
# [inline (always)]
pub fn set_lserdy (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "External Low Speed oscillator bypass"]
# [inline (always)]
pub const fn lsebyp (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "External Low Speed oscillator bypass"]
# [inline (always)]
pub fn set_lsebyp (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } # [doc = "LSE oscillator drive capability"]
# [inline (always)]
pub const fn lsedrv (& self) -> super :: vals :: Lsedrv { let val = (self . 0 >> 3usize) & 0x03 ; super :: vals :: Lsedrv :: from_bits (val as u8) } # [doc = "LSE oscillator drive capability"]
# [inline (always)]
pub fn set_lsedrv (& mut self , val : super :: vals :: Lsedrv) { self . 0 = (self . 0 & ! (0x03 << 3usize)) | (((val . to_bits () as u32) & 0x03) << 3usize) ; } # [doc = "RTC clock source selection"]
# [inline (always)]
pub const fn rtcsel (& self) -> super :: vals :: Rtcsel { let val = (self . 0 >> 8usize) & 0x03 ; super :: vals :: Rtcsel :: from_bits (val as u8) } # [doc = "RTC clock source selection"]
# [inline (always)]
pub fn set_rtcsel (& mut self , val : super :: vals :: Rtcsel) { self . 0 = (self . 0 & ! (0x03 << 8usize)) | (((val . to_bits () as u32) & 0x03) << 8usize) ; } # [doc = "RTC clock enable"]
# [inline (always)]
pub const fn rtcen (& self) -> bool { let val = (self . 0 >> 15usize) & 0x01 ; val != 0 } # [doc = "RTC clock enable"]
# [inline (always)]
pub fn set_rtcen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize) ; } # [doc = "Backup domain software reset"]
# [inline (always)]
pub const fn bdrst (& self) -> bool { let val = (self . 0 >> 16usize) & 0x01 ; val != 0 } # [doc = "Backup domain software reset"]
# [inline (always)]
pub fn set_bdrst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize) ; } } impl Default for Bdcr { # [inline (always)]
fn default () -> Bdcr { Bdcr (0) } } # [doc = "Clock configuration register (RCC_CFGR)"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Cfgr (pub u32) ; impl Cfgr { # [doc = "System clock Switch"]
# [inline (always)]
pub const fn sw (& self) -> super :: vals :: Sw { let val = (self . 0 >> 0usize) & 0x03 ; super :: vals :: Sw :: from_bits (val as u8) } # [doc = "System clock Switch"]
# [inline (always)]
pub fn set_sw (& mut self , val : super :: vals :: Sw) { self . 0 = (self . 0 & ! (0x03 << 0usize)) | (((val . to_bits () as u32) & 0x03) << 0usize) ; } # [doc = "System Clock Switch Status"]
# [inline (always)]
pub const fn sws (& self) -> super :: vals :: Sw { let val = (self . 0 >> 2usize) & 0x03 ; super :: vals :: Sw :: from_bits (val as u8) } # [doc = "System Clock Switch Status"]
# [inline (always)]
pub fn set_sws (& mut self , val : super :: vals :: Sw) { self . 0 = (self . 0 & ! (0x03 << 2usize)) | (((val . to_bits () as u32) & 0x03) << 2usize) ; } # [doc = "AHB prescaler"]
# [inline (always)]
pub const fn hpre (& self) -> super :: vals :: Hpre { let val = (self . 0 >> 4usize) & 0x0f ; super :: vals :: Hpre :: from_bits (val as u8) } # [doc = "AHB prescaler"]
# [inline (always)]
pub fn set_hpre (& mut self , val : super :: vals :: Hpre) { self . 0 = (self . 0 & ! (0x0f << 4usize)) | (((val . to_bits () as u32) & 0x0f) << 4usize) ; } # [doc = "APB Low speed prescaler (APB1)"]
# [inline (always)]
pub const fn ppre (& self) -> super :: vals :: Ppre { let val = (self . 0 >> 8usize) & 0x07 ; super :: vals :: Ppre :: from_bits (val as u8) } # [doc = "APB Low speed prescaler (APB1)"]
# [inline (always)]
pub fn set_ppre (& mut self , val : super :: vals :: Ppre) { self . 0 = (self . 0 & ! (0x07 << 8usize)) | (((val . to_bits () as u32) & 0x07) << 8usize) ; } # [doc = "APCPRE is deprecated. See ADC field in CFGR2 register."]
# [inline (always)]
pub const fn adcpre (& self) -> bool { let val = (self . 0 >> 14usize) & 0x01 ; val != 0 } # [doc = "APCPRE is deprecated. See ADC field in CFGR2 register."]
# [inline (always)]
pub fn set_adcpre (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize) ; } # [doc = "PLL input clock source"]
# [inline (always)]
pub const fn pllsrc (& self) -> super :: vals :: Pllsrc { let val = (self . 0 >> 15usize) & 0x03 ; super :: vals :: Pllsrc :: from_bits (val as u8) } # [doc = "PLL input clock source"]
# [inline (always)]
pub fn set_pllsrc (& mut self , val : super :: vals :: Pllsrc) { self . 0 = (self . 0 & ! (0x03 << 15usize)) | (((val . to_bits () as u32) & 0x03) << 15usize) ; } # [doc = "HSE divider for PLL entry. Same bit as PREDIV\\[0\\]
from CFGR2 register. Refer to it for its meaning"]
# [inline (always)]
pub const fn pllxtpre (& self) -> super :: vals :: Pllxtpre { let val = (self . 0 >> 17usize) & 0x01 ; super :: vals :: Pllxtpre :: from_bits (val as u8) } # [doc = "HSE divider for PLL entry. Same bit as PREDIV\\[0\\]
from CFGR2 register. Refer to it for its meaning"]
# [inline (always)]
pub fn set_pllxtpre (& mut self , val : super :: vals :: Pllxtpre) { self . 0 = (self . 0 & ! (0x01 << 17usize)) | (((val . to_bits () as u32) & 0x01) << 17usize) ; } # [doc = "PLL Multiplication Factor"]
# [inline (always)]
pub const fn pllmul (& self) -> super :: vals :: Pllmul { let val = (self . 0 >> 18usize) & 0x0f ; super :: vals :: Pllmul :: from_bits (val as u8) } # [doc = "PLL Multiplication Factor"]
# [inline (always)]
pub fn set_pllmul (& mut self , val : super :: vals :: Pllmul) { self . 0 = (self . 0 & ! (0x0f << 18usize)) | (((val . to_bits () as u32) & 0x0f) << 18usize) ; } # [doc = "Microcontroller clock output"]
# [inline (always)]
pub const fn mcosel (& self) -> super :: vals :: Mcosel { let val = (self . 0 >> 24usize) & 0x0f ; super :: vals :: Mcosel :: from_bits (val as u8) } # [doc = "Microcontroller clock output"]
# [inline (always)]
pub fn set_mcosel (& mut self , val : super :: vals :: Mcosel) { self . 0 = (self . 0 & ! (0x0f << 24usize)) | (((val . to_bits () as u32) & 0x0f) << 24usize) ; } # [doc = "Microcontroller Clock Output Prescaler"]
# [inline (always)]
pub const fn mcopre (& self) -> super :: vals :: Mcopre { let val = (self . 0 >> 28usize) & 0x07 ; super :: vals :: Mcopre :: from_bits (val as u8) } # [doc = "Microcontroller Clock Output Prescaler"]
# [inline (always)]
pub fn set_mcopre (& mut self , val : super :: vals :: Mcopre) { self . 0 = (self . 0 & ! (0x07 << 28usize)) | (((val . to_bits () as u32) & 0x07) << 28usize) ; } # [doc = "PLL clock not divided for MCO"]
# [inline (always)]
pub const fn pllmcodiv (& self) -> super :: vals :: Pllmcodiv { let val = (self . 0 >> 31usize) & 0x01 ; super :: vals :: Pllmcodiv :: from_bits (val as u8) } # [doc = "PLL clock not divided for MCO"]
# [inline (always)]
pub fn set_pllmcodiv (& mut self , val : super :: vals :: Pllmcodiv) { self . 0 = (self . 0 & ! (0x01 << 31usize)) | (((val . to_bits () as u32) & 0x01) << 31usize) ; } } impl Default for Cfgr { # [inline (always)]
fn default () -> Cfgr { Cfgr (0) } } # [doc = "Clock configuration register 2"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Cfgr2 (pub u32) ; impl Cfgr2 { # [doc = "PREDIV division factor"]
# [inline (always)]
pub const fn prediv (& self) -> super :: vals :: Prediv { let val = (self . 0 >> 0usize) & 0x0f ; super :: vals :: Prediv :: from_bits (val as u8) } # [doc = "PREDIV division factor"]
# [inline (always)]
pub fn set_prediv (& mut self , val : super :: vals :: Prediv) { self . 0 = (self . 0 & ! (0x0f << 0usize)) | (((val . to_bits () as u32) & 0x0f) << 0usize) ; } } impl Default for Cfgr2 { # [inline (always)]
fn default () -> Cfgr2 { Cfgr2 (0) } } # [doc = "Clock configuration register 3"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Cfgr3 (pub u32) ; impl Cfgr3 { # [doc = "USART1 clock source selection"]
# [inline (always)]
pub const fn usart1sw (& self) -> super :: vals :: Usart1sw { let val = (self . 0 >> 0usize) & 0x03 ; super :: vals :: Usart1sw :: from_bits (val as u8) } # [doc = "USART1 clock source selection"]
# [inline (always)]
pub fn set_usart1sw (& mut self , val : super :: vals :: Usart1sw) { self . 0 = (self . 0 & ! (0x03 << 0usize)) | (((val . to_bits () as u32) & 0x03) << 0usize) ; } # [doc = "I2C1 clock source selection"]
# [inline (always)]
pub const fn i2c1sw (& self) -> super :: vals :: Icsw { let val = (self . 0 >> 4usize) & 0x01 ; super :: vals :: Icsw :: from_bits (val as u8) } # [doc = "I2C1 clock source selection"]
# [inline (always)]
pub fn set_i2c1sw (& mut self , val : super :: vals :: Icsw) { self . 0 = (self . 0 & ! (0x01 << 4usize)) | (((val . to_bits () as u32) & 0x01) << 4usize) ; } # [doc = "HDMI CEC clock source selection"]
# [inline (always)]
pub const fn cecsw (& self) -> super :: vals :: Cecsw { let val = (self . 0 >> 6usize) & 0x01 ; super :: vals :: Cecsw :: from_bits (val as u8) } # [doc = "HDMI CEC clock source selection"]
# [inline (always)]
pub fn set_cecsw (& mut self , val : super :: vals :: Cecsw) { self . 0 = (self . 0 & ! (0x01 << 6usize)) | (((val . to_bits () as u32) & 0x01) << 6usize) ; } # [doc = "USB clock source selection"]
# [inline (always)]
pub const fn usbsw (& self) -> super :: vals :: Usbsw { let val = (self . 0 >> 7usize) & 0x01 ; super :: vals :: Usbsw :: from_bits (val as u8) } # [doc = "USB clock source selection"]
# [inline (always)]
pub fn set_usbsw (& mut self , val : super :: vals :: Usbsw) { self . 0 = (self . 0 & ! (0x01 << 7usize)) | (((val . to_bits () as u32) & 0x01) << 7usize) ; } # [doc = "ADCSW is deprecated. See ADC field in CFGR2 register."]
# [inline (always)]
pub const fn adcsw (& self) -> bool { let val = (self . 0 >> 8usize) & 0x01 ; val != 0 } # [doc = "ADCSW is deprecated. See ADC field in CFGR2 register."]
# [inline (always)]
pub fn set_adcsw (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize) ; } # [doc = "USART2 clock source selection"]
# [inline (always)]
pub const fn usart2sw (& self) -> super :: vals :: Usartsw { let val = (self . 0 >> 16usize) & 0x03 ; super :: vals :: Usartsw :: from_bits (val as u8) } # [doc = "USART2 clock source selection"]
# [inline (always)]
pub fn set_usart2sw (& mut self , val : super :: vals :: Usartsw) { self . 0 = (self . 0 & ! (0x03 << 16usize)) | (((val . to_bits () as u32) & 0x03) << 16usize) ; } # [doc = "USART3 clock source"]
# [inline (always)]
pub const fn usart3sw (& self) -> super :: vals :: Usartsw { let val = (self . 0 >> 18usize) & 0x03 ; super :: vals :: Usartsw :: from_bits (val as u8) } # [doc = "USART3 clock source"]
# [inline (always)]
pub fn set_usart3sw (& mut self , val : super :: vals :: Usartsw) { self . 0 = (self . 0 & ! (0x03 << 18usize)) | (((val . to_bits () as u32) & 0x03) << 18usize) ; } } impl Default for Cfgr3 { # [inline (always)]
fn default () -> Cfgr3 { Cfgr3 (0) } } # [doc = "Clock interrupt register (RCC_CIR)"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Cir (pub u32) ; impl Cir { # [doc = "LSI Ready Interrupt flag"]
# [inline (always)]
pub const fn lsirdyf (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "LSI Ready Interrupt flag"]
# [inline (always)]
pub fn set_lsirdyf (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "LSE Ready Interrupt flag"]
# [inline (always)]
pub const fn lserdyf (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "LSE Ready Interrupt flag"]
# [inline (always)]
pub fn set_lserdyf (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "HSI Ready Interrupt flag"]
# [inline (always)]
pub const fn hsirdyf (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "HSI Ready Interrupt flag"]
# [inline (always)]
pub fn set_hsirdyf (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } # [doc = "HSE Ready Interrupt flag"]
# [inline (always)]
pub const fn hserdyf (& self) -> bool { let val = (self . 0 >> 3usize) & 0x01 ; val != 0 } # [doc = "HSE Ready Interrupt flag"]
# [inline (always)]
pub fn set_hserdyf (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize) ; } # [doc = "PLL Ready Interrupt flag"]
# [inline (always)]
pub const fn pllrdyf (& self) -> bool { let val = (self . 0 >> 4usize) & 0x01 ; val != 0 } # [doc = "PLL Ready Interrupt flag"]
# [inline (always)]
pub fn set_pllrdyf (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize) ; } # [doc = "HSI14 ready interrupt flag"]
# [inline (always)]
pub const fn hsi14rdyf (& self) -> bool { let val = (self . 0 >> 5usize) & 0x01 ; val != 0 } # [doc = "HSI14 ready interrupt flag"]
# [inline (always)]
pub fn set_hsi14rdyf (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize) ; } # [doc = "HSI48 ready interrupt flag"]
# [inline (always)]
pub const fn hsi48rdyf (& self) -> bool { let val = (self . 0 >> 6usize) & 0x01 ; val != 0 } # [doc = "HSI48 ready interrupt flag"]
# [inline (always)]
pub fn set_hsi48rdyf (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize) ; } # [doc = "Clock Security System Interrupt flag"]
# [inline (always)]
pub const fn cssf (& self) -> bool { let val = (self . 0 >> 7usize) & 0x01 ; val != 0 } # [doc = "Clock Security System Interrupt flag"]
# [inline (always)]
pub fn set_cssf (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize) ; } # [doc = "LSI Ready Interrupt Enable"]
# [inline (always)]
pub const fn lsirdyie (& self) -> bool { let val = (self . 0 >> 8usize) & 0x01 ; val != 0 } # [doc = "LSI Ready Interrupt Enable"]
# [inline (always)]
pub fn set_lsirdyie (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize) ; } # [doc = "LSE Ready Interrupt Enable"]
# [inline (always)]
pub const fn lserdyie (& self) -> bool { let val = (self . 0 >> 9usize) & 0x01 ; val != 0 } # [doc = "LSE Ready Interrupt Enable"]
# [inline (always)]
pub fn set_lserdyie (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize) ; } # [doc = "HSI Ready Interrupt Enable"]
# [inline (always)]
pub const fn hsirdyie (& self) -> bool { let val = (self . 0 >> 10usize) & 0x01 ; val != 0 } # [doc = "HSI Ready Interrupt Enable"]
# [inline (always)]
pub fn set_hsirdyie (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize) ; } # [doc = "HSE Ready Interrupt Enable"]
# [inline (always)]
pub const fn hserdyie (& self) -> bool { let val = (self . 0 >> 11usize) & 0x01 ; val != 0 } # [doc = "HSE Ready Interrupt Enable"]
# [inline (always)]
pub fn set_hserdyie (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize) ; } # [doc = "PLL Ready Interrupt Enable"]
# [inline (always)]
pub const fn pllrdyie (& self) -> bool { let val = (self . 0 >> 12usize) & 0x01 ; val != 0 } # [doc = "PLL Ready Interrupt Enable"]
# [inline (always)]
pub fn set_pllrdyie (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize) ; } # [doc = "HSI14 ready interrupt enable"]
# [inline (always)]
pub const fn hsi14rdyie (& self) -> bool { let val = (self . 0 >> 13usize) & 0x01 ; val != 0 } # [doc = "HSI14 ready interrupt enable"]
# [inline (always)]
pub fn set_hsi14rdyie (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize) ; } # [doc = "HSI48 ready interrupt enable"]
# [inline (always)]
pub const fn hsi48rdyie (& self) -> bool { let val = (self . 0 >> 14usize) & 0x01 ; val != 0 } # [doc = "HSI48 ready interrupt enable"]
# [inline (always)]
pub fn set_hsi48rdyie (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize) ; } # [doc = "LSI Ready Interrupt Clear"]
# [inline (always)]
pub const fn lsirdyc (& self) -> bool { let val = (self . 0 >> 16usize) & 0x01 ; val != 0 } # [doc = "LSI Ready Interrupt Clear"]
# [inline (always)]
pub fn set_lsirdyc (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize) ; } # [doc = "LSE Ready Interrupt Clear"]
# [inline (always)]
pub const fn lserdyc (& self) -> bool { let val = (self . 0 >> 17usize) & 0x01 ; val != 0 } # [doc = "LSE Ready Interrupt Clear"]
# [inline (always)]
pub fn set_lserdyc (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize) ; } # [doc = "HSI Ready Interrupt Clear"]
# [inline (always)]
pub const fn hsirdyc (& self) -> bool { let val = (self . 0 >> 18usize) & 0x01 ; val != 0 } # [doc = "HSI Ready Interrupt Clear"]
# [inline (always)]
pub fn set_hsirdyc (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize) ; } # [doc = "HSE Ready Interrupt Clear"]
# [inline (always)]
pub const fn hserdyc (& self) -> bool { let val = (self . 0 >> 19usize) & 0x01 ; val != 0 } # [doc = "HSE Ready Interrupt Clear"]
# [inline (always)]
pub fn set_hserdyc (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize) ; } # [doc = "PLL Ready Interrupt Clear"]
# [inline (always)]
pub const fn pllrdyc (& self) -> bool { let val = (self . 0 >> 20usize) & 0x01 ; val != 0 } # [doc = "PLL Ready Interrupt Clear"]
# [inline (always)]
pub fn set_pllrdyc (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize) ; } # [doc = "HSI 14 MHz Ready Interrupt Clear"]
# [inline (always)]
pub const fn hsi14rdyc (& self) -> bool { let val = (self . 0 >> 21usize) & 0x01 ; val != 0 } # [doc = "HSI 14 MHz Ready Interrupt Clear"]
# [inline (always)]
pub fn set_hsi14rdyc (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize) ; } # [doc = "HSI48 Ready Interrupt Clear"]
# [inline (always)]
pub const fn hsi48rdyc (& self) -> bool { let val = (self . 0 >> 22usize) & 0x01 ; val != 0 } # [doc = "HSI48 Ready Interrupt Clear"]
# [inline (always)]
pub fn set_hsi48rdyc (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize) ; } # [doc = "Clock security system interrupt clear"]
# [inline (always)]
pub const fn cssc (& self) -> bool { let val = (self . 0 >> 23usize) & 0x01 ; val != 0 } # [doc = "Clock security system interrupt clear"]
# [inline (always)]
pub fn set_cssc (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize) ; } } impl Default for Cir { # [inline (always)]
fn default () -> Cir { Cir (0) } } # [doc = "Clock control register"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Cr (pub u32) ; impl Cr { # [doc = "Internal High Speed clock enable"]
# [inline (always)]
pub const fn hsion (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "Internal High Speed clock enable"]
# [inline (always)]
pub fn set_hsion (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "Internal High Speed clock ready flag"]
# [inline (always)]
pub const fn hsirdy (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "Internal High Speed clock ready flag"]
# [inline (always)]
pub fn set_hsirdy (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "Internal High Speed clock trimming"]
# [inline (always)]
pub const fn hsitrim (& self) -> u8 { let val = (self . 0 >> 3usize) & 0x1f ; val as u8 } # [doc = "Internal High Speed clock trimming"]
# [inline (always)]
pub fn set_hsitrim (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x1f << 3usize)) | (((val as u32) & 0x1f) << 3usize) ; } # [doc = "Internal High Speed clock Calibration"]
# [inline (always)]
pub const fn hsical (& self) -> u8 { let val = (self . 0 >> 8usize) & 0xff ; val as u8 } # [doc = "Internal High Speed clock Calibration"]
# [inline (always)]
pub fn set_hsical (& mut self , val : u8) { self . 0 = (self . 0 & ! (0xff << 8usize)) | (((val as u32) & 0xff) << 8usize) ; } # [doc = "External High Speed clock enable"]
# [inline (always)]
pub const fn hseon (& self) -> bool { let val = (self . 0 >> 16usize) & 0x01 ; val != 0 } # [doc = "External High Speed clock enable"]
# [inline (always)]
pub fn set_hseon (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize) ; } # [doc = "External High Speed clock ready flag"]
# [inline (always)]
pub const fn hserdy (& self) -> bool { let val = (self . 0 >> 17usize) & 0x01 ; val != 0 } # [doc = "External High Speed clock ready flag"]
# [inline (always)]
pub fn set_hserdy (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize) ; } # [doc = "External High Speed clock Bypass"]
# [inline (always)]
pub const fn hsebyp (& self) -> bool { let val = (self . 0 >> 18usize) & 0x01 ; val != 0 } # [doc = "External High Speed clock Bypass"]
# [inline (always)]
pub fn set_hsebyp (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize) ; } # [doc = "Clock Security System enable"]
# [inline (always)]
pub const fn csson (& self) -> bool { let val = (self . 0 >> 19usize) & 0x01 ; val != 0 } # [doc = "Clock Security System enable"]
# [inline (always)]
pub fn set_csson (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize) ; } # [doc = "PLL enable"]
# [inline (always)]
pub const fn pllon (& self) -> bool { let val = (self . 0 >> 24usize) & 0x01 ; val != 0 } # [doc = "PLL enable"]
# [inline (always)]
pub fn set_pllon (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize) ; } # [doc = "PLL clock ready flag"]
# [inline (always)]
pub const fn pllrdy (& self) -> bool { let val = (self . 0 >> 25usize) & 0x01 ; val != 0 } # [doc = "PLL clock ready flag"]
# [inline (always)]
pub fn set_pllrdy (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize) ; } } impl Default for Cr { # [inline (always)]
fn default () -> Cr { Cr (0) } } # [doc = "Clock control register 2"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Cr2 (pub u32) ; impl Cr2 { # [doc = "HSI14 clock enable"]
# [inline (always)]
pub const fn hsi14on (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "HSI14 clock enable"]
# [inline (always)]
pub fn set_hsi14on (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "HR14 clock ready flag"]
# [inline (always)]
pub const fn hsi14rdy (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "HR14 clock ready flag"]
# [inline (always)]
pub fn set_hsi14rdy (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "HSI14 clock request from ADC disable"]
# [inline (always)]
pub const fn hsi14dis (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "HSI14 clock request from ADC disable"]
# [inline (always)]
pub fn set_hsi14dis (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } # [doc = "HSI14 clock trimming"]
# [inline (always)]
pub const fn hsi14trim (& self) -> u8 { let val = (self . 0 >> 3usize) & 0x1f ; val as u8 } # [doc = "HSI14 clock trimming"]
# [inline (always)]
pub fn set_hsi14trim (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x1f << 3usize)) | (((val as u32) & 0x1f) << 3usize) ; } # [doc = "HSI14 clock calibration"]
# [inline (always)]
pub const fn hsi14cal (& self) -> u8 { let val = (self . 0 >> 8usize) & 0xff ; val as u8 } # [doc = "HSI14 clock calibration"]
# [inline (always)]
pub fn set_hsi14cal (& mut self , val : u8) { self . 0 = (self . 0 & ! (0xff << 8usize)) | (((val as u32) & 0xff) << 8usize) ; } # [doc = "HSI48 clock enable"]
# [inline (always)]
pub const fn hsi48on (& self) -> bool { let val = (self . 0 >> 16usize) & 0x01 ; val != 0 } # [doc = "HSI48 clock enable"]
# [inline (always)]
pub fn set_hsi48on (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize) ; } # [doc = "HSI48 clock ready flag"]
# [inline (always)]
pub const fn hsi48rdy (& self) -> bool { let val = (self . 0 >> 17usize) & 0x01 ; val != 0 } # [doc = "HSI48 clock ready flag"]
# [inline (always)]
pub fn set_hsi48rdy (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize) ; } # [doc = "HSI48 factory clock calibration"]
# [inline (always)]
pub const fn hsi48cal (& self) -> u8 { let val = (self . 0 >> 24usize) & 0xff ; val as u8 } # [doc = "HSI48 factory clock calibration"]
# [inline (always)]
pub fn set_hsi48cal (& mut self , val : u8) { self . 0 = (self . 0 & ! (0xff << 24usize)) | (((val as u32) & 0xff) << 24usize) ; } } impl Default for Cr2 { # [inline (always)]
fn default () -> Cr2 { Cr2 (0) } } # [doc = "Control/status register (RCC_CSR)"]
# [repr (transparent)]
# [derive (Copy , Clone , Eq , PartialEq)]
pub struct Csr (pub u32) ; impl Csr { # [doc = "Internal low speed oscillator enable"]
# [inline (always)]
pub const fn lsion (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "Internal low speed oscillator enable"]
# [inline (always)]
pub fn set_lsion (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "Internal low speed oscillator ready"]
# [inline (always)]
pub const fn lsirdy (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "Internal low speed oscillator ready"]
# [inline (always)]
pub fn set_lsirdy (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "1.8 V domain reset flag"]
# [inline (always)]
pub const fn v18pwrrstf (& self) -> bool { let val = (self . 0 >> 23usize) & 0x01 ; val != 0 } # [doc = "1.8 V domain reset flag"]
# [inline (always)]
pub fn set_v18pwrrstf (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize) ; } # [doc = "Remove reset flag"]
# [inline (always)]
pub const fn rmvf (& self) -> bool { let val = (self . 0 >> 24usize) & 0x01 ; val != 0 } # [doc = "Remove reset flag"]
# [inline (always)]
pub fn set_rmvf (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize) ; } # [doc = "Option byte loader reset flag"]
# [inline (always)]
pub const fn oblrstf (& self) -> bool { let val = (self . 0 >> 25usize) & 0x01 ; val != 0 } # [doc = "Option byte loader reset flag"]
# [inline (always)]
pub fn set_oblrstf (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize) ; } # [doc = "PIN reset flag"]
# [inline (always)]
pub const fn pinrstf (& self) -> bool { let val = (self . 0 >> 26usize) & 0x01 ; val != 0 } # [doc = "PIN reset flag"]
# [inline (always)]
pub fn set_pinrstf (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize) ; } # [doc = "POR/PDR reset flag"]
# [inline (always)]
pub const fn porrstf (& self) -> bool { let val = (self . 0 >> 27usize) & 0x01 ; val != 0 } # [doc = "POR/PDR reset flag"]
# [inline (always)]
pub fn set_porrstf (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize) ; } # [doc = "Software reset flag"]
# [inline (always)]
pub const fn sftrstf (& self) -> bool { let val = (self . 0 >> 28usize) & 0x01 ; val != 0 } # [doc = "Software reset flag"]
# [inline (always)]
pub fn set_sftrstf (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize) ; } # [doc = "Independent watchdog reset flag"]
# [inline (always)]
pub const fn iwdgrstf (& self) -> bool { let val = (self . 0 >> 29usize) & 0x01 ; val != 0 } # [doc = "Independent watchdog reset flag"]
# [inline (always)]
pub fn set_iwdgrstf (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize) ; } # [doc = "Window watchdog reset flag"]
# [inline (always)]
pub const fn wwdgrstf (& self) -> bool { let val = (self . 0 >> 30usize) & 0x01 ; val != 0 } # [doc = "Window watchdog reset flag"]
# [inline (always)]
pub fn set_wwdgrstf (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize) ; } # [doc = "Low-power reset flag"]
# [inline (always)]
pub const fn lpwrrstf (& self) -> bool { let val = (self . 0 >> 31usize) & 0x01 ; val != 0 } # [doc = "Low-power reset flag"]
# [inline (always)]
pub fn set_lpwrrstf (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize) ; } } impl Default for Csr { # [inline (always)]
fn default () -> Csr { Csr (0) } } } pub mod vals { # [repr (u8)]
# [derive (Copy , Clone , Eq , PartialEq , Ord , PartialOrd)]
pub enum Cecsw { # [doc = "HSI clock divided by 244 selected as CEC clock source"]
HSI_DIV_244 = 0x0 , # [doc = "LSE clock selected as CEC clock source"]
LSE = 0x01 , } impl Cecsw { # [inline (always)]
pub const fn from_bits (val : u8) -> Cecsw { unsafe { core :: mem :: transmute (val & 0x01) } } # [inline (always)]
pub const fn to_bits (self) -> u8 { unsafe { core :: mem :: transmute (self) } } } impl From < u8 > for Cecsw { # [inline (always)]
fn from (val : u8) -> Cecsw { Cecsw :: from_bits (val) } } impl From < Cecsw > for u8 { # [inline (always)]
fn from (val : Cecsw) -> u8 { Cecsw :: to_bits (val) } } # [repr (u8)]
# [derive (Copy , Clone , Eq , PartialEq , Ord , PartialOrd)]
pub enum Hpre { # [doc = "SYSCLK not divided"]
DIV1 = 0x0 , _RESERVED_1 = 0x01 , _RESERVED_2 = 0x02 , _RESERVED_3 = 0x03 , _RESERVED_4 = 0x04 , _RESERVED_5 = 0x05 , _RESERVED_6 = 0x06 , _RESERVED_7 = 0x07 , # [doc = "SYSCLK divided by 2"]
DIV2 = 0x08 , # [doc = "SYSCLK divided by 4"]
DIV4 = 0x09 , # [doc = "SYSCLK divided by 8"]
DIV8 = 0x0a , # [doc = "SYSCLK divided by 16"]
DIV16 = 0x0b , # [doc = "SYSCLK divided by 64"]
DIV64 = 0x0c , # [doc = "SYSCLK divided by 128"]
DIV128 = 0x0d , # [doc = "SYSCLK divided by 256"]
DIV256 = 0x0e , # [doc = "SYSCLK divided by 512"]
DIV512 = 0x0f , } impl Hpre { # [inline (always)]
pub const fn from_bits (val : u8) -> Hpre { unsafe { core :: mem :: transmute (val & 0x0f) } } # [inline (always)]
pub const fn to_bits (self) -> u8 { unsafe { core :: mem :: transmute (self) } } } impl From < u8 > for Hpre { # [inline (always)]
fn from (val : u8) -> Hpre { Hpre :: from_bits (val) } } impl From < Hpre > for u8 { # [inline (always)]
fn from (val : Hpre) -> u8 { Hpre :: to_bits (val) } } # [repr (u8)]
# [derive (Copy , Clone , Eq , PartialEq , Ord , PartialOrd)]
pub enum Icsw { # [doc = "HSI clock selected as I2C clock source"]
HSI = 0x0 , # [doc = "SYSCLK clock selected as I2C clock source"]
SYS = 0x01 , } impl Icsw { # [inline (always)]
pub const fn from_bits (val : u8) -> Icsw { unsafe { core :: mem :: transmute (val & 0x01) } } # [inline (always)]
pub const fn to_bits (self) -> u8 { unsafe { core :: mem :: transmute (self) } } } impl From < u8 > for Icsw { # [inline (always)]
fn from (val : u8) -> Icsw { Icsw :: from_bits (val) } } impl From < Icsw > for u8 { # [inline (always)]
fn from (val : Icsw) -> u8 { Icsw :: to_bits (val) } } # [repr (u8)]
# [derive (Copy , Clone , Eq , PartialEq , Ord , PartialOrd)]
pub enum Lsedrv { # [doc = "Low driving capability"]
LOW = 0x0 , # [doc = "Medium high driving capability"]
MEDIUMHIGH = 0x01 , # [doc = "Medium low driving capability"]
MEDIUMLOW = 0x02 , # [doc = "High driving capability"]
HIGH = 0x03 , } impl Lsedrv { # [inline (always)]
pub const fn from_bits (val : u8) -> Lsedrv { unsafe { core :: mem :: transmute (val & 0x03) } } # [inline (always)]
pub const fn to_bits (self) -> u8 { unsafe { core :: mem :: transmute (self) } } } impl From < u8 > for Lsedrv { # [inline (always)]
fn from (val : u8) -> Lsedrv { Lsedrv :: from_bits (val) } } impl From < Lsedrv > for u8 { # [inline (always)]
fn from (val : Lsedrv) -> u8 { Lsedrv :: to_bits (val) } } # [repr (u8)]
# [derive (Copy , Clone , Eq , PartialEq , Ord , PartialOrd)]
pub enum Mcopre { # [doc = "MCO is divided by 1"]
DIV1 = 0x0 , # [doc = "MCO is divided by 2"]
DIV2 = 0x01 , # [doc = "MCO is divided by 4"]
DIV4 = 0x02 , # [doc = "MCO is divided by 8"]
DIV8 = 0x03 , # [doc = "MCO is divided by 16"]
DIV16 = 0x04 , # [doc = "MCO is divided by 32"]
DIV32 = 0x05 , # [doc = "MCO is divided by 64"]
DIV64 = 0x06 , # [doc = "MCO is divided by 128"]
DIV128 = 0x07 , } impl Mcopre { # [inline (always)]
pub const fn from_bits (val : u8) -> Mcopre { unsafe { core :: mem :: transmute (val & 0x07) } } # [inline (always)]
pub const fn to_bits (self) -> u8 { unsafe { core :: mem :: transmute (self) } } } impl From < u8 > for Mcopre { # [inline (always)]
fn from (val : u8) -> Mcopre { Mcopre :: from_bits (val) } } impl From < Mcopre > for u8 { # [inline (always)]
fn from (val : Mcopre) -> u8 { Mcopre :: to_bits (val) } } # [repr (u8)]
# [derive (Copy , Clone , Eq , PartialEq , Ord , PartialOrd)]
pub enum Mcosel { # [doc = "MCO output disabled, no clock on MCO"]
DISABLE = 0x0 , # [doc = "Internal RC 14 MHz (HSI14) oscillator clock selected"]
HSI14 = 0x01 , # [doc = "Internal low speed (LSI) oscillator clock selected"]
LSI = 0x02 , # [doc = "External low speed (LSE) oscillator clock selected"]
LSE = 0x03 , # [doc = "System clock selected"]
SYS = 0x04 , # [doc = "Internal RC 8 MHz (HSI) oscillator clock selected"]
HSI = 0x05 , # [doc = "External 4-32 MHz (HSE) oscillator clock selected"]
HSE = 0x06 , # [doc = "PLL clock selected (divided by 1 or 2, depending en PLLMCODIV)"]
PLL = 0x07 , # [doc = "Internal RC 48 MHz (HSI48) oscillator clock selected"]
HSI48 = 0x08 , _RESERVED_9 = 0x09 , _RESERVED_a = 0x0a , _RESERVED_b = 0x0b , _RESERVED_c = 0x0c , _RESERVED_d = 0x0d , _RESERVED_e = 0x0e , _RESERVED_f = 0x0f , } impl Mcosel { # [inline (always)]
pub const fn from_bits (val : u8) -> Mcosel { unsafe { core :: mem :: transmute (val & 0x0f) } } # [inline (always)]
pub const fn to_bits (self) -> u8 { unsafe { core :: mem :: transmute (self) } } } impl From < u8 > for Mcosel { # [inline (always)]
fn from (val : u8) -> Mcosel { Mcosel :: from_bits (val) } } impl From < Mcosel > for u8 { # [inline (always)]
fn from (val : Mcosel) -> u8 { Mcosel :: to_bits (val) } } # [repr (u8)]
# [derive (Copy , Clone , Eq , PartialEq , Ord , PartialOrd)]
pub enum Pllmcodiv { # [doc = "PLL is divided by 2 for MCO"]
DIV2 = 0x0 , # [doc = "PLL is not divided for MCO"]
DIV1 = 0x01 , } impl Pllmcodiv { # [inline (always)]
pub const fn from_bits (val : u8) -> Pllmcodiv { unsafe { core :: mem :: transmute (val & 0x01) } } # [inline (always)]
pub const fn to_bits (self) -> u8 { unsafe { core :: mem :: transmute (self) } } } impl From < u8 > for Pllmcodiv { # [inline (always)]
fn from (val : u8) -> Pllmcodiv { Pllmcodiv :: from_bits (val) } } impl From < Pllmcodiv > for u8 { # [inline (always)]
fn from (val : Pllmcodiv) -> u8 { Pllmcodiv :: to_bits (val) } } # [repr (u8)]
# [derive (Copy , Clone , Eq , PartialEq , Ord , PartialOrd)]
pub enum Pllmul { # [doc = "PLL input clock x2"]
MUL2 = 0x0 , # [doc = "PLL input clock x3"]
MUL3 = 0x01 , # [doc = "PLL input clock x4"]
MUL4 = 0x02 , # [doc = "PLL input clock x5"]
MUL5 = 0x03 , # [doc = "PLL input clock x6"]
MUL6 = 0x04 , # [doc = "PLL input clock x7"]
MUL7 = 0x05 , # [doc = "PLL input clock x8"]
MUL8 = 0x06 , # [doc = "PLL input clock x9"]
MUL9 = 0x07 , # [doc = "PLL input clock x10"]
MUL10 = 0x08 , # [doc = "PLL input clock x11"]
MUL11 = 0x09 , # [doc = "PLL input clock x12"]
MUL12 = 0x0a , # [doc = "PLL input clock x13"]
MUL13 = 0x0b , # [doc = "PLL input clock x14"]
MUL14 = 0x0c , # [doc = "PLL input clock x15"]
MUL15 = 0x0d , # [doc = "PLL input clock x16"]
MUL16 = 0x0e , _RESERVED_f = 0x0f , } impl Pllmul { # [inline (always)]
pub const fn from_bits (val : u8) -> Pllmul { unsafe { core :: mem :: transmute (val & 0x0f) } } # [inline (always)]
pub const fn to_bits (self) -> u8 { unsafe { core :: mem :: transmute (self) } } } impl From < u8 > for Pllmul { # [inline (always)]
fn from (val : u8) -> Pllmul { Pllmul :: from_bits (val) } } impl From < Pllmul > for u8 { # [inline (always)]
fn from (val : Pllmul) -> u8 { Pllmul :: to_bits (val) } } # [repr (u8)]
# [derive (Copy , Clone , Eq , PartialEq , Ord , PartialOrd)]
pub enum Pllsrc { # [doc = "HSI divided by 2 selected as PLL input clock"]
HSI_DIV2 = 0x0 , # [doc = "HSI divided by PREDIV selected as PLL input clock"]
HSI_DIV_PREDIV = 0x01 , # [doc = "HSE divided by PREDIV selected as PLL input clock"]
HSE_DIV_PREDIV = 0x02 , # [doc = "HSI48 divided by PREDIV selected as PLL input clock"]
HSI48_DIV_PREDIV = 0x03 , } impl Pllsrc { # [inline (always)]
pub const fn from_bits (val : u8) -> Pllsrc { unsafe { core :: mem :: transmute (val & 0x03) } } # [inline (always)]
pub const fn to_bits (self) -> u8 { unsafe { core :: mem :: transmute (self) } } } impl From < u8 > for Pllsrc { # [inline (always)]
fn from (val : u8) -> Pllsrc { Pllsrc :: from_bits (val) } } impl From < Pllsrc > for u8 { # [inline (always)]
fn from (val : Pllsrc) -> u8 { Pllsrc :: to_bits (val) } } # [repr (u8)]
# [derive (Copy , Clone , Eq , PartialEq , Ord , PartialOrd)]
pub enum Pllxtpre { # [doc = "HSE clock not divided"]
DIV1 = 0x0 , # [doc = "HSE clock divided by 2"]
DIV2 = 0x01 , } impl Pllxtpre { # [inline (always)]
pub const fn from_bits (val : u8) -> Pllxtpre { unsafe { core :: mem :: transmute (val & 0x01) } } # [inline (always)]
pub const fn to_bits (self) -> u8 { unsafe { core :: mem :: transmute (self) } } } impl From < u8 > for Pllxtpre { # [inline (always)]
fn from (val : u8) -> Pllxtpre { Pllxtpre :: from_bits (val) } } impl From < Pllxtpre > for u8 { # [inline (always)]
fn from (val : Pllxtpre) -> u8 { Pllxtpre :: to_bits (val) } } # [repr (u8)]
# [derive (Copy , Clone , Eq , PartialEq , Ord , PartialOrd)]
pub enum Ppre { # [doc = "HCLK not divided"]
DIV1 = 0x0 , _RESERVED_1 = 0x01 , _RESERVED_2 = 0x02 , _RESERVED_3 = 0x03 , # [doc = "HCLK divided by 2"]
DIV2 = 0x04 , # [doc = "HCLK divided by 4"]
DIV4 = 0x05 , # [doc = "HCLK divided by 8"]
DIV8 = 0x06 , # [doc = "HCLK divided by 16"]
DIV16 = 0x07 , } impl Ppre { # [inline (always)]
pub const fn from_bits (val : u8) -> Ppre { unsafe { core :: mem :: transmute (val & 0x07) } } # [inline (always)]
pub const fn to_bits (self) -> u8 { unsafe { core :: mem :: transmute (self) } } } impl From < u8 > for Ppre { # [inline (always)]
fn from (val : u8) -> Ppre { Ppre :: from_bits (val) } } impl From < Ppre > for u8 { # [inline (always)]
fn from (val : Ppre) -> u8 { Ppre :: to_bits (val) } } # [repr (u8)]
# [derive (Copy , Clone , Eq , PartialEq , Ord , PartialOrd)]
pub enum Prediv { # [doc = "PREDIV input clock not divided"]
DIV1 = 0x0 , # [doc = "PREDIV input clock divided by 2"]
DIV2 = 0x01 , # [doc = "PREDIV input clock divided by 3"]
DIV3 = 0x02 , # [doc = "PREDIV input clock divided by 4"]
DIV4 = 0x03 , # [doc = "PREDIV input clock divided by 5"]
DIV5 = 0x04 , # [doc = "PREDIV input clock divided by 6"]
DIV6 = 0x05 , # [doc = "PREDIV input clock divided by 7"]
DIV7 = 0x06 , # [doc = "PREDIV input clock divided by 8"]
DIV8 = 0x07 , # [doc = "PREDIV input clock divided by 9"]
DIV9 = 0x08 , # [doc = "PREDIV input clock divided by 10"]
DIV10 = 0x09 , # [doc = "PREDIV input clock divided by 11"]
DIV11 = 0x0a , # [doc = "PREDIV input clock divided by 12"]
DIV12 = 0x0b , # [doc = "PREDIV input clock divided by 13"]
DIV13 = 0x0c , # [doc = "PREDIV input clock divided by 14"]
DIV14 = 0x0d , # [doc = "PREDIV input clock divided by 15"]
DIV15 = 0x0e , # [doc = "PREDIV input clock divided by 16"]
DIV16 = 0x0f , } impl Prediv { # [inline (always)]
pub const fn from_bits (val : u8) -> Prediv { unsafe { core :: mem :: transmute (val & 0x0f) } } # [inline (always)]
pub const fn to_bits (self) -> u8 { unsafe { core :: mem :: transmute (self) } } } impl From < u8 > for Prediv { # [inline (always)]
fn from (val : u8) -> Prediv { Prediv :: from_bits (val) } } impl From < Prediv > for u8 { # [inline (always)]
fn from (val : Prediv) -> u8 { Prediv :: to_bits (val) } } # [repr (u8)]
# [derive (Copy , Clone , Eq , PartialEq , Ord , PartialOrd)]
pub enum Rtcsel { # [doc = "No clock"]
DISABLE = 0x0 , # [doc = "LSE oscillator clock used as RTC clock"]
LSE = 0x01 , # [doc = "LSI oscillator clock used as RTC clock"]
LSI = 0x02 , # [doc = "HSE oscillator clock divided by a prescaler used as RTC clock"]
HSE = 0x03 , } impl Rtcsel { # [inline (always)]
pub const fn from_bits (val : u8) -> Rtcsel { unsafe { core :: mem :: transmute (val & 0x03) } } # [inline (always)]
pub const fn to_bits (self) -> u8 { unsafe { core :: mem :: transmute (self) } } } impl From < u8 > for Rtcsel { # [inline (always)]
fn from (val : u8) -> Rtcsel { Rtcsel :: from_bits (val) } } impl From < Rtcsel > for u8 { # [inline (always)]
fn from (val : Rtcsel) -> u8 { Rtcsel :: to_bits (val) } } # [repr (u8)]
# [derive (Copy , Clone , Eq , PartialEq , Ord , PartialOrd)]
pub enum Sw { # [doc = "HSI oscillator used as system clock"]
HSI = 0x0 , # [doc = "HSE oscillator used as system clock"]
HSE = 0x01 , # [doc = "PLL used as system clock"]
PLL1_P = 0x02 , # [doc = "HSI48 used as system clock"]
HSI48 = 0x03 , } impl Sw { # [inline (always)]
pub const fn from_bits (val : u8) -> Sw { unsafe { core :: mem :: transmute (val & 0x03) } } # [inline (always)]
pub const fn to_bits (self) -> u8 { unsafe { core :: mem :: transmute (self) } } } impl From < u8 > for Sw { # [inline (always)]
fn from (val : u8) -> Sw { Sw :: from_bits (val) } } impl From < Sw > for u8 { # [inline (always)]
fn from (val : Sw) -> u8 { Sw :: to_bits (val) } } # [repr (u8)]
# [derive (Copy , Clone , Eq , PartialEq , Ord , PartialOrd)]
pub enum Usart1sw { # [doc = "PCLK selected as USART clock source"]
PCLK2 = 0x0 , # [doc = "SYSCLK selected as USART clock source"]
SYS = 0x01 , # [doc = "LSE selected as USART clock source"]
LSE = 0x02 , # [doc = "HSI selected as USART clock source"]
HSI = 0x03 , } impl Usart1sw { # [inline (always)]
pub const fn from_bits (val : u8) -> Usart1sw { unsafe { core :: mem :: transmute (val & 0x03) } } # [inline (always)]
pub const fn to_bits (self) -> u8 { unsafe { core :: mem :: transmute (self) } } } impl From < u8 > for Usart1sw { # [inline (always)]
fn from (val : u8) -> Usart1sw { Usart1sw :: from_bits (val) } } impl From < Usart1sw > for u8 { # [inline (always)]
fn from (val : Usart1sw) -> u8 { Usart1sw :: to_bits (val) } } # [repr (u8)]
# [derive (Copy , Clone , Eq , PartialEq , Ord , PartialOrd)]
pub enum Usartsw { # [doc = "PCLK selected as USART clock source"]
PCLK1 = 0x0 , # [doc = "SYSCLK selected as USART clock source"]
SYS = 0x01 , # [doc = "LSE selected as USART clock source"]
LSE = 0x02 , # [doc = "HSI selected as USART clock source"]
HSI = 0x03 , } impl Usartsw { # [inline (always)]
pub const fn from_bits (val : u8) -> Usartsw { unsafe { core :: mem :: transmute (val & 0x03) } } # [inline (always)]
pub const fn to_bits (self) -> u8 { unsafe { core :: mem :: transmute (self) } } } impl From < u8 > for Usartsw { # [inline (always)]
fn from (val : u8) -> Usartsw { Usartsw :: from_bits (val) } } impl From < Usartsw > for u8 { # [inline (always)]
fn from (val : Usartsw) -> u8 { Usartsw :: to_bits (val) } } # [repr (u8)]
# [derive (Copy , Clone , Eq , PartialEq , Ord , PartialOrd)]
pub enum Usbsw { # [doc = "HSI48 selected as USB clock source"]
HSI48 = 0x0 , # [doc = "PLL clock selected as USB clock source"]
PLL1_P = 0x01 , } impl Usbsw { # [inline (always)]
pub const fn from_bits (val : u8) -> Usbsw { unsafe { core :: mem :: transmute (val & 0x01) } } # [inline (always)]
pub const fn to_bits (self) -> u8 { unsafe { core :: mem :: transmute (self) } } } impl From < u8 > for Usbsw { # [inline (always)]
fn from (val : u8) -> Usbsw { Usbsw :: from_bits (val) } } impl From < Usbsw > for u8 { # [inline (always)]
fn from (val : Usbsw) -> u8 { Usbsw :: to_bits (val) } } }