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100# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 15:09:40 May 01, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# fakequidditch_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEMA5F31C6
set_global_assignment -name TOP_LEVEL_ENTITY fakequidditch
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:09:39 MAY 01, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR "C:/Users/Cansu/Desktop/fakequidditch/simulation/qsim/" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation
set_location_assignment PIN_B13 -to blue[0]
set_location_assignment PIN_G13 -to blue[1]
set_location_assignment PIN_H13 -to blue[2]
set_location_assignment PIN_F14 -to blue[3]
set_location_assignment PIN_AF14 -to clk
set_location_assignment PIN_J9 -to green[0]
set_location_assignment PIN_J10 -to green[1]
set_location_assignment PIN_H12 -to green[2]
set_location_assignment PIN_G10 -to green[3]
set_location_assignment PIN_B11 -to hor_sync
set_location_assignment PIN_A13 -to red[0]
set_location_assignment PIN_C13 -to red[1]
set_location_assignment PIN_E13 -to red[2]
set_location_assignment PIN_B12 -to red[3]
set_location_assignment PIN_W15 -to team1_vd_button
set_location_assignment PIN_Y16 -to team1_vu_button
set_location_assignment PIN_AA14 -to team2_vd_button
set_location_assignment PIN_AA15 -to team2_vu_button
set_location_assignment PIN_D11 -to ver_sync
set_location_assignment PIN_F15 -to blue[5]
set_location_assignment PIN_G15 -to blue[6]
set_location_assignment PIN_J14 -to blue[7]
set_location_assignment PIN_G11 -to green[4]
set_location_assignment PIN_G12 -to green[5]
set_location_assignment PIN_F11 -to green[6]
set_location_assignment PIN_E11 -to green[7]
set_location_assignment PIN_C12 -to red[4]
set_location_assignment PIN_D12 -to red[5]
set_location_assignment PIN_E12 -to red[6]
set_location_assignment PIN_F13 -to red[7]
set_location_assignment PIN_H14 -to blue[4]
set_location_assignment PIN_A11 -to vga_clk
set_global_assignment -name VERILOG_FILE fakequidditch.v
set_global_assignment -name VERILOG_FILE vga_controller/vga_controller.v
set_global_assignment -name VERILOG_FILE game_controller/game_controller.v
set_global_assignment -name VERILOG_FILE game_controller/ver_player_controller.v
set_global_assignment -name VERILOG_FILE board.v
set_global_assignment -name VERILOG_FILE game_controller/ball_controller_cansu.v
set_global_assignment -name VERILOG_FILE game_controller/hor_player_controller.v
set_global_assignment -name VERILOG_FILE game_controller/bludger_controller.v
set_location_assignment PIN_AF20 -to team2_hr_button
set_location_assignment PIN_AG18 -to team1_hl_button
set_location_assignment PIN_AF18 -to team1_hr_button
set_location_assignment PIN_AF19 -to team2_hl_button
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top